A parameter for modern low power digital designs, in particular for microcontroller based applications like portable or mobile electronic devices, is the current consumption in a low power mode. In low power designs, the leakage of digital gates is a contributor to the current consumption in the low power mode. For modern electronic devices which are manufactured using deep submicron process technologies, leakage currents are becoming a dominating factor. In today's low power digital designs, power gating of electronic domains (i.e. circuits) is an approach to reduce power consumption while keeping the system operable. According to the power gating approach, a digital circuit is disconnected from the power supply once it is not needed. However, in order to provide available resources and sophisticated operability of the electronic device, fast wake-up times are required for the respective electronic domain. During wake-up or power-up of the electronic domain, the local voltage level has to rise as fast as possible. However, considerable electric charge has to be transferred especially to the load capacitance of the electronic domain. This may lead to temporary high inrush currents which may cause two major problems. First, there may be a voltage drop at the power supply lines in the electronic device due to charge shifting effects. This may affect already active domains and may cause a temporary violation of the minimum supply voltage specification. Second, modern deep submicron processed electronic devices frequently use a low drop out voltage power supply (LDO). An LDO is available to deliver a limited maximum output current and may get overloaded by high inrush currents.
FIG. 1 is a simplified circuit diagram showing a detailed view of a power-gated electronic device, according to the prior art. A plurality of digital domains 10 is coupled to a power supply network which is coupled to a positive supply rail 12 supplying a positive supply voltage VDD and to a negative supply rail 14 for supplying a negative supply voltage VSS to the respective digital domains 10.
At the positive supply rail 12, the power supply network is interrupted using a plurality of switches acting as power gates 13. By selectively setting the respective power gate 13 to a conductive or non-conductive state, one or more of the digital domains 10 may be powered-up or may be disconnected from the power supply, for example in a low power mode. Each power 13 gate comprises a strong switch 16 and a weak switch 18. The strong switch 16 and the weak switch 18 offer different electric conductivity. For example, the strong 16 and weak 18 switches may be transistors having a different width. The weak switch 18 acts as a current limiting device for limiting inrush currents from the power supply network to the digital domain 10. The strong switch 16 provides a low resistance electrical connection of the digital domain 10 and minimizes losses during normal operation of the respective digital domain 10.
Upon power-on of a digital domain 10, first, the weak switch or switches 18 are closed upon communication of the signal PON. Once the supply voltage and current are settled, the strong switch 16 takes over the power supply and is set to a conductive state by the signal PGOOD. However, timing and dimensioning of the strong and weak switches 16, 18 has to be adjusted to the characteristics of the digital domain 10 and the available power supply of the electronic device and accurate timing between the signals PON and PGOOD is a rather difficult task. Further, there is a strong dependence on process variations, operating temperatures and the selected supply voltage level VDD. This will either lead to long and unacceptable power-up times of the digital domains 10 or may cause high dynamic currents that may overload the power supply, in particular an LDO.